How fixing max trans on clock path will impact timing {setup and hold}?

Ans: Fixing trans on clock path by up-sizing of buffers or inserting of buffers will decrease the insertion delay of a Flip-Flop.

Now consider the impact of insertion delay of FF on timing...........

Setup requirement equation:

tlaunch_insertion_delay + tcq + tcomb < tclk - tsetup + tcapture_insertion_delay

Hold requirement equation:

tlaunch_insertion_delay + tcq + tcomb > thold + tcapture_insertion_delay

Scenario-1: 

                 if u fix trans on diverge capture path it is going to worsen the setup requirement  and improves the hold requirement.

Scenario-2:

                if u fix trans on diverge launch path it is going to worsen the hold requirement and improves the setup requirement.

Scenario-3:

               if u fix trans on common path for launch & capture it is not going to show any impact on timing

Note: Fixing trans is going to show impact on skew

Tutorial for Bash shell

http://www.iitk.ac.in/LDP/LDP/abs/html/abs-guide.html

What "Levels of Logic" parameter refers in CTS report_QoR is?

This is the number of combinational logic cells present in the worst timing 
path. reports the number of logic levels by counting the number of times the attribute "@is_combinational" is set to "true" for the cells in the worst timing path.

What are power gating cells, and why are retention registers sometimes referred to as power gating cells?

Answer:

Power gating cells, also known as MTCMOS cells, power switch cells, power 
switches, or power management cells, are special library cells that act as a 
connection point between two voltage rails when they are turned on and a break 
point in the current path between the two rails when they are turned off. 
Turning off the power gating cells causes the switched rail (also known as the 
internal rail) to be disconnected from its source, or primary rail, which 
removes power from all cells connected to that switched rail. 

Power gating cells exist on the power or ground rails of one or more blocks in 
a design. They are either user-instantiated or inserted by either Jupiter-XT or 
IC Compiler. A power gating cell that switches the power net is sometimes 
referred to as a "header" cell, and a power gating cell that switches the 
ground net is sometimes referred to as a "footer" cell. 

Retention registers, by contrast, are a special form of sequential cell that 
can retain its state when the primary power net of the power domain's block 
(in which the cell exists) is powered down. Retention registers retain state 
by having two voltage rail pins: the primary voltage rail pin, which supplies 
power to the cell in its normal operating state, and the secondary (or backup) 
voltage rail pin, which supplies power to a low leakage state-saving latch 
within the sequential cell when the primary power is switched off.

Some versions of retention registers are known as State Retention Power Gating 
cells (or SRPG's), which is why retention registers are sometimes referred to as 
power gating cells. For clarity, it is recommended that you refer to state-saving
sequential cells as retention registers, and refer to the cells that connect and
disconnect a primary rail from a switched rail as power switches or power gates.

Handling complexities in clock gating checks

http://www.techonlineindia.com/article/12-07-16/handling_complexities_in_clock_gating_checks.aspx

study about spare cells

http://chipdesignart.wordpress.com/2007/12/20/study-about-spare-cells/

creating excel sheet using perl

http://search.cpan.org/~jmcnamara/Excel-Writer-XLSX-0.02/lib/Excel/Writer/XLSX/Examples.pm#Example:_a_simple.pl

vlsi Question Bank links

http://www.rficdesign.com/vlsi-interview-question

http://basicvlsi.blogspot.in/p/vls-interview-questions.html

http://vlsitech.blogspot.in/2008/07/vlsi-interview-questionspart-2.html

http://longer.spaces.eepw.com.cn/articles/article/item/43381

http://www.scribd.com/doc/60738241/1/Companywise-ASIC-VLSI-Interview-Questions

http://vlsichip.blogspot.in/

http://ashokkrishna.blogspot.in/2010/07/vlsi-interview-questions.html
 

library file information site

Technology file: http://rfic.eecs.berkeley.edu/~niknejad/doc-05-26-02/techfile.html

Library file: http://ece451web.groups.et.byu.net/cadence-help/tutorial_CharCell/index.html

Synopsys online tutorial link

http://venividiwiki.ee.virginia.edu/mediawiki/index.php/ToolsSynopsysTutorialsBasicICC

http://www.scribd.com/doc/54534835/Synopsis-PNR

Diff between global hard keep out and soft keep out?

Hard Blockage: placement blockage used to block the placement of cells around the macro with specific offset from macro boundaries (4 sides)..

Soft Blockage: It is kind of placement blockage used to block the placement of cells around the macro with specific offset from macro boundaries.. but can allows the cell placement of cells during placement optimization & placement legalization..

Here Global refers to all the macros in the design with fixed attribute...

blog sites

http://vlsi-concept.blogspot.in/

http://www.aoni.waseda.jp/chensong/icc.htm

http://neeasic.blogspot.in/

http://www.scribd.com/doc/35951235/2007-12-ICC-Incremental-Training#download

http://only-vlsi.blogspot.in/

http://vlsi-expert.blogspot.in/2011/02/synopsys-design-constraints-sdc-basics.html

http://www.scribd.com/doc/36518023/On-Chip-Variation-and-CRPR

http://www.scribd.com/doc/76417776/Physical-Design-Complete

http://lofi.forum.physorg.com/Power-planning_5683.html

http://wenku.baidu.com/view/094c5827af45b307e871972f.html

http://chipverification.blogspot.in/search/label/VLSI

http://wenku.baidu.com/view/094c5827af45b307e871972f.html - power optimization techniques

http://www.synopsys.com.cn/information/snug/2010/design-quality-check

http://www.asic.co.in/DesignGuidlinesRTLcoding.htm

Multi-Corner Multi-Mode

What's MCMM

MCMM stands for: Multi-Corner Multi-Mode (static timing analysis used in the design of digital ICs)

What's a Mode

A mode is defined by a set of clocks, supply voltages, timing constraints, and libraries. It can also have annotation data, such as SDF or parasitics files.
Many chip have multiple modes such as functional modes, test mode, sleep mode, and etc.

What's a Corner

A corner is defined as a set of libraries characterized for process, voltage, and temperature variations.
Corners are not dependent on functional settings; they are meant to capture variations in the manufacturing process, along with expected variations in the voltage and temperature of the environment in which the chip will operate.

complete knowledge on STA follow below link

http://wenku.baidu.com/view/818eefdace2f0066f533228a.html?from=rec&pos=1&weight=8&lastweight=3&count=5

What is cloning and buffering?

Answer:

• Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell.
• Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease the dealy.

What are clock tree types?

Answer:
H tree, Balanced tree, X tree, Clustering tree, Fish bone

What is latency? Give the types?

Answer:

1. Source Latency:

• It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".
• Delay from clock source to beginning of clock tree (i.e. clock definition point).
• The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

1. Network latency:

• It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".

• The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

What is IR drop? How to avoid? How it affects timing?

Answer:

• There is a resistance associated with each metal layer. This resistance consumes power causing voltage drop i.e.IR drop.
• If IR drop is more==>delay increases.

How delays are characterized using WLM (Wire Load Model)?

Answer:

For a given wireload model the delay are estimated based on the number of fanout of the cell driving the net.

Fanout vs net length is tabulated in WLMs.

Values of unit resistance R and unit capacitance C are given in technology file.

Net length varies based on the fanout number.

Once the net length is known delay can be calculated; Sometimes it is again tabulated.

What are several factors to improve propagation delay of standard cell?

Answer:

• Improve the input transition to the cell under consideration by up sizing the driver.
• Reduce the load seen by the cell under consideration, either by placement refinement or buffering.
• If allowed increase the drive strength or replace with LVT (low threshold voltage) cell.

Why do you use alternate routing approach HVH/VHV (Horizontal-Vertical-Horizontal/ Vertical-Horizontal-Vertical)?

Answer:

This approach allows routability of the design and better usage of routing resources.

Why power stripes routed in the top metal layers?

The resistivity of top metal layers are less and hence less IR drop is seen in power distribution network. If power stripes are routed in lower metal layers this will use good amount of lower routing resources and therefore it can create routing congestion.

What is electromigration? Reasons for electromigration? and when it can occur in design?

Electromigration is a phenomenon, it can lead to opens and shorts due to metal ion displacement caused by the flow of electrons in metal, which can lead to functional failure of IC device. Reason for Electromigration is increase in current densities in net, which often occurs when strong cell drives thick net in CTN (Clock Tree Network) or in design.
To prevent this problem use the associate reference cell (a buffer or inverter inserted in CTS stage) with non default rules

 7.What is Different Types of IC packaging ?

 IC are packaged in many types they are: * BGA1* BGA2* Ball grid array* CPGA* Ceramic ball grid array* Cerquad* DIP-8* Die attachment* Dual Flat No Lead* Dual in-line package* Flat pack * Flip chip* Flip-chip pin grid array* HVQFN* LQFP* Land grid array* Leadless chip carrier * Low insertion force* Micro FCBGA* Micro Leadframe Package* MicroLeadFrame* Mini-Cartridge* Multi-Chip Module* OPGA* PQFP* Package on package* Pin grid array* Plastic leaded chip carrier * QFN* QFP* Quadruple in-line package* ROM cartridge* Shrink Small-Outline Package* Single in-line package* Small-Outline Integrated Circuit* Staggered Pin Grid Array* Surface-mount technology* TO220* TO3* TO92* TQFP* TSSOP

* Thin small-outline package* Through-hole technology* UICC* Zig-zag in-line package

CTS

why clock tree needed in synchronous asic design? 
what is clock skew? 
how to improve clock skew? 
what is max insertion delay?
how to improve max insertion delay? 

what is clock tree reference?

what is clock tree reference?


it is any standard cell ( example a buffer or a inverter ) in library used in clock tree synthesis for balancing the skew.

what is differences between Gate Sizing and Transistor Sizing?

what is differences between Gate Sizing and Transistor Sizing? 



GATE sizing and Transistor sizing ineffect mean the same thing. It deals with changing the W/L ratio of the PMOS and NMOS to achieve better performance.

The only difference is that GATE sizing is in DIGITAL domain where you size the GATE, ie, both PMOS and NMOS transistors of a gate (NOT, AND) will be sized in correct proprotions to get the required speed,power, area,etc... Thus the term GATE sizing.

Whereas in Transistor sizing, you modify either the PMOS or the NMOS... You can also modify both the transistors, but there will be no particular relationship between the two when sizing. This is done mostly in ANALOG CMOS design where in we size the transistors to get the desired drive currents,etc.. 

One example of GATE sizing is... an Inverter design. We know that the mobility of an NMOS is approx 3 times that of PMOS.. Thus when designing an inverter, if the W/L ratio of the NMOS is 1 then the W/L ratio of the PMOS will be 3. This is done to make sure that the NMOS and PMOS produce the same amount of output current and also to make sure that the period..rise time and fall time are almost the same. 

what is meant by transistor up-sizing?
          changing the transistor channel width is known as transistor up-sizing, due to this the density of free electron in the channel will increases, so that current flow in the channel increases, so that drive strength of a cell increases.

what is technology node?
technology node is the length of a transistor channel