How fixing max trans on clock path will impact timing {setup and hold}?

Ans: Fixing trans on clock path by up-sizing of buffers or inserting of buffers will decrease the insertion delay of a Flip-Flop.

Now consider the impact of insertion delay of FF on timing...........

Setup requirement equation:

tlaunch_insertion_delay + tcq + tcomb < tclk - tsetup + tcapture_insertion_delay

Hold requirement equation:

tlaunch_insertion_delay + tcq + tcomb > thold + tcapture_insertion_delay

Scenario-1: 

                 if u fix trans on diverge capture path it is going to worsen the setup requirement  and improves the hold requirement.

Scenario-2:

                if u fix trans on diverge launch path it is going to worsen the hold requirement and improves the setup requirement.

Scenario-3:

               if u fix trans on common path for launch & capture it is not going to show any impact on timing

Note: Fixing trans is going to show impact on skew