What is cloning and buffering?

Answer:

• Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell.
• Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease the dealy.

What are clock tree types?

Answer:
H tree, Balanced tree, X tree, Clustering tree, Fish bone

What is latency? Give the types?

Answer:

1. Source Latency:

• It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".
• Delay from clock source to beginning of clock tree (i.e. clock definition point).
• The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

1. Network latency:

• It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".

• The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

What is IR drop? How to avoid? How it affects timing?

Answer:

• There is a resistance associated with each metal layer. This resistance consumes power causing voltage drop i.e.IR drop.
• If IR drop is more==>delay increases.

How delays are characterized using WLM (Wire Load Model)?

Answer:

For a given wireload model the delay are estimated based on the number of fanout of the cell driving the net.

Fanout vs net length is tabulated in WLMs.

Values of unit resistance R and unit capacitance C are given in technology file.

Net length varies based on the fanout number.

Once the net length is known delay can be calculated; Sometimes it is again tabulated.

What are several factors to improve propagation delay of standard cell?

Answer:

• Improve the input transition to the cell under consideration by up sizing the driver.
• Reduce the load seen by the cell under consideration, either by placement refinement or buffering.
• If allowed increase the drive strength or replace with LVT (low threshold voltage) cell.

Why do you use alternate routing approach HVH/VHV (Horizontal-Vertical-Horizontal/ Vertical-Horizontal-Vertical)?

Answer:

This approach allows routability of the design and better usage of routing resources.

Why power stripes routed in the top metal layers?

The resistivity of top metal layers are less and hence less IR drop is seen in power distribution network. If power stripes are routed in lower metal layers this will use good amount of lower routing resources and therefore it can create routing congestion.

What is electromigration? Reasons for electromigration? and when it can occur in design?

Electromigration is a phenomenon, it can lead to opens and shorts due to metal ion displacement caused by the flow of electrons in metal, which can lead to functional failure of IC device. Reason for Electromigration is increase in current densities in net, which often occurs when strong cell drives thick net in CTN (Clock Tree Network) or in design.
To prevent this problem use the associate reference cell (a buffer or inverter inserted in CTS stage) with non default rules

 7.What is Different Types of IC packaging ?

 IC are packaged in many types they are: * BGA1* BGA2* Ball grid array* CPGA* Ceramic ball grid array* Cerquad* DIP-8* Die attachment* Dual Flat No Lead* Dual in-line package* Flat pack * Flip chip* Flip-chip pin grid array* HVQFN* LQFP* Land grid array* Leadless chip carrier * Low insertion force* Micro FCBGA* Micro Leadframe Package* MicroLeadFrame* Mini-Cartridge* Multi-Chip Module* OPGA* PQFP* Package on package* Pin grid array* Plastic leaded chip carrier * QFN* QFP* Quadruple in-line package* ROM cartridge* Shrink Small-Outline Package* Single in-line package* Small-Outline Integrated Circuit* Staggered Pin Grid Array* Surface-mount technology* TO220* TO3* TO92* TQFP* TSSOP

* Thin small-outline package* Through-hole technology* UICC* Zig-zag in-line package

CTS

why clock tree needed in synchronous asic design? 
what is clock skew? 
how to improve clock skew? 
what is max insertion delay?
how to improve max insertion delay? 

what is clock tree reference?

what is clock tree reference?


it is any standard cell ( example a buffer or a inverter ) in library used in clock tree synthesis for balancing the skew.

what is differences between Gate Sizing and Transistor Sizing?

what is differences between Gate Sizing and Transistor Sizing? 



GATE sizing and Transistor sizing ineffect mean the same thing. It deals with changing the W/L ratio of the PMOS and NMOS to achieve better performance.

The only difference is that GATE sizing is in DIGITAL domain where you size the GATE, ie, both PMOS and NMOS transistors of a gate (NOT, AND) will be sized in correct proprotions to get the required speed,power, area,etc... Thus the term GATE sizing.

Whereas in Transistor sizing, you modify either the PMOS or the NMOS... You can also modify both the transistors, but there will be no particular relationship between the two when sizing. This is done mostly in ANALOG CMOS design where in we size the transistors to get the desired drive currents,etc.. 

One example of GATE sizing is... an Inverter design. We know that the mobility of an NMOS is approx 3 times that of PMOS.. Thus when designing an inverter, if the W/L ratio of the NMOS is 1 then the W/L ratio of the PMOS will be 3. This is done to make sure that the NMOS and PMOS produce the same amount of output current and also to make sure that the period..rise time and fall time are almost the same. 

what is meant by transistor up-sizing?
          changing the transistor channel width is known as transistor up-sizing, due to this the density of free electron in the channel will increases, so that current flow in the channel increases, so that drive strength of a cell increases.

what is technology node?
technology node is the length of a transistor channel